Title: ASIC Verification Engineer
Job location: Preference is for Santa Clara, CA / Folsom / Oregon
Term: Long Term contract
Skill set Desirable:
· Greater than 5-6 years of experience in SOC projects.
· Should have experience working in Full chip SOC and unit level validation projects.
· SystemVerilog and OVM and UVM are a must
· Past experience in Intel SoCs is a plus
· x86 experience is a big plus of engineers ( at least for 2 engineers) Understand the concept of random test generation, coverage Familiarity with coverage points and SV assertion HD Languages: Verilog a must
Desirable - scripting languages - Tcl / Perl / Python etc
Thanks,
Deepak Dahiya
IDC Technologies, Inc.
1851 McCarthy Boulevard, Suite 116,Milpitas, CA, USA, 95035
Phone: 408-457-9399 Extn: 2005| Fax: 408-608-6088
Email: deepak.d@idctechnologies.com | Web: www.idctechnologies.com
ISO 9001-2008 Certified
YM: dpk_staffing
GTalk: dpk.recruiter
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