Urgently required: ASIC Physical Design/Structural Design Engineer

Hi Partners,

Kindly let me know if you have any consultant for the following position.

 

Please respond back with an updated resume and all inclusive rates to recruiter@burgeonits.com

 

Position: ASIC Physical Design/Structural Design Engineer

Location: Oregon OR /Santa Clara, CA

Duration: 6 months

 

Skills Preferred

·        Expertise in Netlist to GDS flow which includes Synthesis, Layout (Floorplan, Place and Route, CTS (clock tree synthesis) and  Static Timing Analysis,

·        Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formailty, and Caliber.

·        Work experience in 45nm, 22nm, 14nm, or lower process technology

·        Good knowledge of digital design concepts

·        Good knowledge of ASIC design flow

·        Good team player and ability to work with  stakeholders like RTL team, DFT team and verification teams

·        Good hands on knowledge of Planning and execution at block level and Full chip level

 

Qualifications Basic

Bachelor’s degree or Master’s Degree in Electronics/VLSI/Electrical  Engineering

At least  4 -10 years of experience with below skills set

 

Thanks & Regards

 

Raja
Burgeon IT Services LLC
Phone No. : 302-338-9683; 302-220-4724, Fax : 302-355-1559
Email: recruiter@burgeonits.com
Website: www.burgeonits.com

 

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