Urgent-RTL Design Engineer @ Menlopark,CA

Role: RTL Design Engineer
Location: Menlopark ,CA
Type: Contract

Job Description:

Minimum 5-7 years' experience, FPGA/ASIC RTL Design experience.
Verilog, VHDL, RTL implementation, Linting, CDC, Synthesis/STA, video
codec/processing, H.265" "H.264" "HEVC"
VP9 MP4 MP5.
Contribute to micro-architecture specification for SoC design block.
Participate in SoC Chip Architecture specification reviews.
Interact with SoC integration, verification and physical design teams and
also with IP vendors.
Handle complete responsibility of an entire block starting from
Micro-architecture specifications, RTL implementation, Linting, CDC,
Synthesis/STA.



Technical / Soft Skills

Expertise Level (Expert / Good / Knowledge)

Verilog

Expert

Micro-architecture specifications, RTL implementation, Linting, CDC,
Synthesis/STA

Expert

Video Codec experience

Expert

· Experience in PCIe, HBM memory protocol is preferred

Good

· Good appreciation of AXI/AHB bus protocol, GigBE, USB, NAND
Flash Technology, PCIe Gen2/3 Host interface, DDR2/3 memory interfaces etc.

Good

· "JPEG2000" "J2K" CABAC "VIDEO COMPRESSION" "VIDEO TRANSCODING
ALGORITHM

Good
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*Thanks and Regards,*

*Y.PREMKUMAR*
*Aqua Information Systems Inc.*
*300 N Pottstown Pike, Suite # 130*
*Exton, PA 19341*
*Direct:215-666-6795*
*Fax: 215-600-1617*
*GTalk: recuriter prem. *

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